The CPU Clock Speed

The clock speed of a CPU, measured in gigahertz (GHz), represents the number of cycles a CPU can perform per second. One gigahertz equals one billion cycles per second. Therefore, a CPU with a clock speed of 2.2 GHz can execute 2.2 billion cycles every second while older CPUs had speed measured in megahertz which is millions of cycles per second.

• Clock Cycle:
  • Single Electrical pulse into the CPU.
• Clock Speeds:
  • 1 Hz(Hertz) = It means one clock cycle per second.
  • 1 kilohertz (kHz) = 1,000 Hz = It means one thousand clock cycles per second.
  • 1 Megahertz (MHz) = 1,000,000 Hz = It means one millions clock cycles per second.
  • 1 Gigahertz (GHz) = 1,000,000,000 Hz = It means one billions clock cycles per second.

Each cycle is essentially a pulse from the clock that triggers the CPU to perform a basic operation, such as moving data, performing a computation, or accessing memory. The higher the clock speed, the more operations the CPU can perform in a given period, which generally translates to better performance.

For the Clock speed CPU relies on the external component.

• The CPU clock is provided by a crystal oscillator and is responsible for generating the high-frequency clock signal that drives the CPU's internal operations (executing instructions).
• This clock signal ensures that the CPU executes instructions at a constant and predictable rate, essential for the correct operation of the processor.
• CPU system Clock typically generates high-frequency signal.
• Overclocking:
  • Overclocking is the process of increasing the clock speed of a computer components, typically the CPU or GPU, beyond the manufacturer's specification to achieve better performance.
  • While overclocking can result in higher performance, it also comes with risks and requires careful management of various factors.
  • CPU (Central Processing Unit):
    • The CPU's clock speed determines how many operations it can perform per second. Increasing this speed can make the CPU process data faster.
  • GPU (Graphics Processing Unit):
    • Overclocking the GPU can result in better graphics performance, which is crucial for gaming and graphical rendering tasks.
  • Overclocking settings are usually configured in the BIOS/UEFI firmware of the motherboard. This interface allows you to adjust the clock multiplier, base clock, and voltage settings.

Programmable Interval Timer (PIT)

It is a hardware timer used to generate precise timing intervals and periodic interrupts. It is a separate component from the CPU clock. It generates less frequency, configurable based on required timing intervals (e.g., several kHz).

The very first processor of x86 series 8086 have the Intel 8253 and 8254 chips for the PIT. These provide the programmable timing and interrupt capabilities crucial for system timing, task scheduling, and other time-sensitive operations.

Usage in IBM PC Systems:

• System Timing: The PIT was instrumental in generating periodic interrupts used by the operating system (such as MS-DOS) for maintaining system time and scheduling tasks.
• Real-Time Clock (RTC) Emulation: In some configurations, the PIT could emulate a real-time clock, providing basic timekeeping functionality even when the system was powered off (with battery backup).
• Sound Generation: By programming the PIT in certain modes, it could generate square wave signals used for basic sound generation through the PC speaker.

Legacy and Modern Relevance

• While direct use of the Intel 8253 and 8254 PITs has diminished in modern systems, their principles and functionalities have influenced subsequent timer designs.
• Modern systems now utilize more advanced timers such as the High Precision Event Timer (HPET), Advanced Programmable Interrupt Controller (APIC) timers, and Real-Time Clock (RTC) chips for enhanced timing accuracy and additional features.

8253:

Let's break down what each of these pins and signals typically does:

• D0...D7 (Data Lines):
  • These are the 8-bit data lines connected to the data bus of the system. They are used for reading and writing data and commands to the 8253.
  • These pins carry our data when we are sending or reading data to the controller.  
• CLK 0, CLK 1, CLK 2 (Clock Input Pins):
  • These are the clock input pins for the three independent counters (Counter 0, Counter 1, and Counter 2) within the 8253. Each counter can be connected to a different clock source or operate asynchronously.
• OUT 0, OUT 1, OUT 2 (Output Data Lines):
  • These pins provide the output signals from each of the three counters. Depending on the mode of operation configured for each counter, these outputs can generate different types of signals such as interrupts or square waves.
• GATE 0, GATE 1, GATE 2 (Gate Data Lines):
  • These pins are used in certain operating modes (like Mode 2) to control when the counting should occur. The gate signal can either enable or disable the counting process.
• GND (Ground):
  • Provides the ground reference voltage for the 8253 chip.
• Vcc (Input Voltage):
  • Supplies the operating voltage (typically +5V or +3.3V) to power the 8253 chip.
• WR (Write Enable) and RD (Read Enable):
  • These signals indicate whether the CPU is writing data to or reading data from the 8253 chip, respectively.
    • RD (Read) Pin: When the RD pin is active (low), the 8253 PIT outputs data onto the data bus.
    • WR (Write) Pin: When the WR pin is active (low), the 8253 PIT latches data from the data bus.
• CS (Chip Select Signal):
  • Activates the 8253 chip when asserted, indicating that the CPU intends to communicate with it.
  • It is a special pin that determines what the controller should do with the RD and WR.
  • If the CS pin is "low", the controller will respond to the RD and WR pins. If CS is not, they are ignored. WR and RD connect to the Systems Control Bus. The CS pin connects to the systems Address Bus for port i/o operations.
  • Operation:
    • When the CS pin is low (active), the 8253 PIT is enabled and can respond to the RD and WR signals.
    • When the CS pin is high (inactive), the 8253 PIT is disabled and will ignore any RD and WR signals.
• A0, A1 (Address Lines):
  • These lines are used by the CPU to select which internal register of the 8253 is being accessed. By varying these address lines, the CPU can access the Control Word Register (CW) or the individual counters' data registers.

The 8253 consists of the following components:

1. Data Bus Buffer: This tri-state, bi-directional, 8-bit buffer interfaces the internal data bus with the external system data bus.
2. Read/Write Logic: This block controls the communication between the CPU and the 8253. This component determines whether data is being read from or written to the PIT. It interprets signals from the CPU and directs the data accordingly.
3. Control Word Register: This 8-bit register is used to select the counter, mode, and read/write operations. Used by the CPU to set up the mode of operation for each counter. The control word configures the counter’s mode, binary or BCD counting, and selects which counter is being accessed.
4. Counters: The 8253 has three independent 16-bit counters (Counter 0, Counter 1, Counter 2). Each counter has its own clock input, gate control, and output.
   1. Counter 0: Often used for system clock functions, generating interrupts at regular intervals.
   2. Counter 1: Typically used for dynamic RAM refresh rates.
   3. Counter 2: Used for generating tones or managing other peripheral device timings.

Active-Low Signals (RD, WR):

In digital electronics, active-low signals are common. These signals are considered active when they are low (0) and inactive when they are high (1). This convention is used for the 8253 PIT's control signals:

• RD (Read Enable): Active when 0, meaning a read operation is taking place.
• WR (Write Enable): Active when 0, meaning a write operation is taking place.

Address Decoding: The system’s address bus determines if the 8253 PIT is selected. If the address corresponds to the PIT, the CS pin is pulled low.

Chip Select (CS):

• If CS is low, the 8253 PIT is enabled.
• If CS is high, the 8253 PIT is disabled and will ignore any further signals on the RD and WR pins.

Read/Write Operations:

• Write Operation:
  1. The CPU places data on the data bus.
  2. The WR pin is pulled low, indicating a write operation.
  3. If CS is low, the 8253 PIT latches the data from the data bus into the appropriate register (control word register or counter register).
• Read Operation:
  1. The RD pin is pulled low, indicating a read operation.
  2. If CS is low, the 8253 PIT places the requested data onto the data bus for the CPU to read.

Timer | Channel | Counter:

Have you notices that there are three groups of the CLK, OUT, and GATE pins. They are there for a reason. 8253 microcontroller contain 3 independent timers.

They are used for different purposes within the system and each counter is of 16 bit in size.

• The Intel 8253 PIT includes three independent 16-bit programmable counters or "channels" labeled as Counter 0, Counter 1, and Counter 2.
• Each Counter is used for different purpose.
• Each Counter has its own clock input, gate control, and output.

Counter 0 (System Timer):

• Connection: The OUT pin of Counter 0 is typically connected to the 8259 Programmable Interrupt Controller (PIC). Since it is connected to the interrupt with the lowest number (IRQ0) it also has the highest priority over all other hardware interrupts.
• Purpose: It generates periodic interrupts for the system timer.
• Usage: This is used by the operating system to keep track of time, manage multitasking, and perform other timing-related tasks.
• Operation: Often set to Mode 2 (Rate Generator) to generate a continuous stream of interrupts at a fixed interval.

Counter 1 (DRAM Refresh):

• Connection: The OUT pin of Counter 1 is often connected to the memory controller.
• Purpose: It generates a timing signal for refreshing DRAM memory.
• Usage: Dynamic RAM (DRAM) requires periodic refresh cycles to maintain data integrity. The signal from Counter 1 ensures that the refresh operations are performed at regular intervals.
• Operation: Typically set to Mode 2 (Rate Generator) to produce a steady refresh signal.

Counter 3 (Speaker Tone Generator):

• Connection: The OUT pin of Counter 2 is connected to the PC speaker.
• Purpose: It generates audio tones.
• Usage: This counter can be used to produce sound effects or simple melodies by generating square wave signals of varying frequencies.
• Operation: Often set to Mode 3 (Square Wave Generator) to produce a square wave output that can drive the speaker.

Channel Modes:

Each counter can be programmed with different modes. This is done by sending in Initialization Control Word(ICW) to the controller.

Mode 0 (Interrupt on Terminal Count):

The counter is loaded with an initial count and decrements with each clock pulse. When it reaches zero, an interrupt is generated, and the output goes low.

How Mode 0 Works

• Initialization:
  • The counter is loaded with an initial COUNT value.
  • The OUT pin is set low initially.
• Counting:
  • The counter decrements the COUNT value on each clock pulse (CLK signal).
  • Counting starts one clock cycle after the COUNT value is programmed into the counter.
• Terminal Count:
  • When the COUNT value reaches zero, the OUT pin is set high.
  • The OUT pin remains high until the counter is reloaded with a new value or the control word is rewritten.
• Reinitialization:
  • To reuse the counter, a new COUNT value must be loaded or a new control word must be written to the control register.

Clock (CLK):   ___|¯|___|¯|___|¯|___|¯|___|¯|___|¯|___|¯|___|¯|___|¯|___
               /     \ /     \ /     \ /     \ /     \ /     \ /     \
COUNT       :  N      N-1    N-2      ...     3       2       1       0
               |_______|_______|_______|______|_______|_______|_______|

OUT         :  ______________________________________________________|¯|____

Example: Generating an Interrupt Every 10 Milliseconds

Assume we want to generate an interrupt every 10 milliseconds using the 8253/8254 PIT with a clock frequency of 1 MHz (1 microsecond per clock cycle).

Step-by-Step Setup:

• Calculate the COUNT Value:
  • To generate an interrupt every 10 milliseconds:
    • 10 milliseconds = 10,000 microseconds.
  • Therefore, the COUNT value should be 10,000.
• Program the PIT:
  • Write the control word and COUNT value to the PIT.
• Configure Mode 0:
  • Set the PIT to Mode 0 (Interrupt on Terminal Count).
• Operation:
  • When the counter reaches 0, the OUT pin will go high, signaling an interrupt.
• Reinitialization:
  • Reload the COUNT value 10,000 to repeat the process.

Mode 1: Hardware Triggered One-Shot

Mode 2: Rate Generator:

This mode is typically used for generating a continuous pulse waveform. The counter decrements on each clock pulse, and when it reaches zero, it reloads the initial count and starts again, generating a periodic waveform.

Mode 3: Square Wave Generator:

Similar to Mode 2, but the output is a square wave. The counter counts down to zero, toggles the output, and reloads the count to start again.

Mode 4: Software Triggered Strobe:

The counter starts counting from the initial value, and when it reaches zero, it generates a single pulse at the output.

Mode 5: Hardware Triggered Strobe:

Similar to Mode 4, but the counting is initiated by a trigger via the gate input.

Registers:

All other port addresses from 0x44-0x4f are undefined.

• RD (Read Line): Activates to read the selected register’s content.
• WR (Write Line): Activates to write data into the selected register.
• A0, A1 (Address Lines): Select which register (Counter 0, 1, 2, or Control Word) is being accessed.
• Loading (Write): Allows setting an initial count value into the counter register.
• Reading: Retrieves the current count value from the counter register.

Counter 0:

• Port Address: 0x40
• Functionality:
  • Load Operation (Write):
    • When WR (Write Line) is active (WR = 0 (inactive), RD = 1 (active), A0 = 0, A1 = 0), Counter 0 is loaded with an initial count value provided on the data bus (D0…D7).
  • Read Operation:
    • When RD (Read Line) is active (RD = 0, WR = 1 (inactive), A0 = 0, A1 = 0), reads the current count value from Counter 0 and placed onto the data bus (D0…D7). The CPU then reads this value from the data bus.

Counter 1:

• Port Address: 0x41
• Functionality:
  • Load Operation (Write):
    • When WR is active (WR = 0 (active), RD = 1 (inactive), A0 = 1, A1 = 0), Counter 1 is loaded with an initial count value from the data bus
  • Read Operation:
    • When RD is active (RD = 0 (active), WR = 1 (inactive), A0 = 1, A1 = 0), reads the current count value from Counter 1 and place in the data bus

Counter 2:

• Port Address: 0x42
• Functionality:
  • Load Operation (Write):
    • When WR is active (WR = 0 (active), RD = 1 (inactive), A0 = 0, A1 = 1), Counter 2 is loaded with an initial count value.
  • Read Operation:
    • When RD is active (RD = 0 (active), WR = 1 (inactive), A0 = 0, A1 = 1), reads the current count value from Counter 2.

Example Usage:

• Writing to Counter 0:
  • A0 = 0, A1 = 0 to select Counter 0.
  • Activate WR with low (Because down counter) to write an initial count value into Counter 0.
• Reading from Counter 1:
  • A0 = 0, A1 = 1 select Counter 1.
  • Activate RD with low to read the current count value from Counter 1.

Handling 16-bit Data with an 8-bit Bus:

The bus of 8253 is of 8 bit ranging from (A0 - A7). However the counter registers are 16-bit wide.

• Before writing or reading from the counter registers, a control word must be sent to the PIT.
  • The control word specifies:
    • Which counter register (Counter 0, 1, 2) to access.
    • Whether the operation is a read or write.
    • Other configuration settings such as operating mode and counting method.
• Addressing withing Counter Register:
  • The PIT uses additional control lines (A0, A1) alongside the control word to address specific bytes within the 16-bit counter registers.
  • These control lines determine which byte (high byte or low byte) of the 16-bit register is being accessed:
    • A0 = 0, A1 = 0: Low byte (least significant byte) of the 16-bit counter register.
    • A0 = 0, A1 = 1: High byte (most significant byte) of the 16-bit counter register.
• Data Bus Limitation:
  • The PIT's data bus (D0-D7) can only transfer 8 bits of data at a time.
  • Therefore, when writing a 16-bit value into a counter register, two consecutive write operations are required:
    • First, write the low byte of the 16-bit value.
    • Then, write the high byte of the 16-bit value.
• Reading Data:
  • Similarly, when reading a 16-bit value from a counter register, two consecutive read operations are performed:
    • First, read the low byte.
    • Then, read the high byte.
• Example:
  • To write a 16-bit value (e.g., 0xABCD) into Counter 0:
    • Send a control word specifying Counter 0 and write operation.
    • Send the low byte (0xCD) to the PIT.
    • Send the high byte (0xAB) to the PIT.
  • Reading a 16-bit value from Counter 1:
    • Send a control word specifying Counter 1 and read operation.
    • Read the low byte from the PIT.
    • Read the high byte from the PIT.

Control Word Register (8-bit register):

The Control Word Register is used to specify the operation mode, access mode, and counter mode for each of the three timers (Counter 0, Counter 1, and Counter 2). This register can only be written to, not read from. The control word must be written before using the counters.

The Control Word Register is an 8-bit register with the following format:

 D7  D6  D5  D4  D3  D2  D1  D0
 SC1 SC0 RW1 RW0 M2  M1  M0  BCD

• Bit Breakdown
  • SC1, SC0 (Select Counter): These bits determine which counter is being configured.
    • 00 - Counter 0
    • 01 - Counter 1
    • 10 - Counter 2
    • 11 - Read-back command (only for 8254, not 8253)
  • RW1, RW0 (Read/Write Mode): These bits specify how the counter value will be accessed.
    • 00 - Counter Latch Command (latch current counter value)
    • 01 - Read/Write least significant byte only
    • 10 - Read/Write most significant byte only
    • 11 - Read/Write least significant byte first, then most significant byte
  • M2, M1, M0 (Mode): These bits specify the operating mode of the counter.
    • 000 - Mode 0 (Interrupt on Terminal Count)
    • 001 - Mode 1 (Hardware Re-triggerable One-Shot)
    • 010 - Mode 2 (Rate Generator)
    • 011 - Mode 3 (Square Wave Generator)
    • 100 - Mode 4 (Software Triggered Strobe)
    • 101 - Mode 5 (Hardware Triggered Strobe)
    • 110 and 111 - Same as Mode 2 and Mode 3, respectively (for 8254)
  • BCD (Binary/Decimal): This bit determines the counting mode.
    • 0 - 16-bit binary (default)
    • 1 - 4-digit Binary Coded Decimal (BCD)

Writing to the Control Word Register:

To write the control word to the PIT, the following steps are typically performed:

• Select the Control Word Register:
  • Set the address lines A0 and A1 to the appropriate values to select the Control Word Register.
  • Typically, A0 = 1 and A1 = 1.
• Enable Write Operation:
  • Enable the RD line with high and WR line with low (because of down counter) to indicate a write operation.
  • Ensure the CS (Chip Select) line is active to select the PIT.
• Write the Control Word:
  • Place the control word on the data bus (D0...D7).
  • The control word is then written into the Control Word Register of the selected counter.

Example:

For instance, if you want to configure Counter 0 to operate in Mode 2 (Rate Generator) with a read/load operation for both LSB and MSB, you would set the Control Word Register as follows:

• SC1, SC0: 00 (Counter 0)
• RW1, RW0: 11 (Read/Load LSB first, then MSB)
• M2, M1, M0: 010 (Mode 2 - Rate Generator)
• BCD: 0 (16-bit binary)

The binary representation of this control word would be:

  | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 |

Create a Timer for 5 Second in 8253

ISR: First a thing to consider, you must setup ISR to handle the timer interrupt. In protected mode, the CPU relies on the IDT(Interrupt Descriptor Table) to determine how to handle interrupts. The IDT is a table that defines the interrupt services routines (ISRs) for various interrupt vectors. Without a properly configured IDT, the CPU will not know where to transfer control when an interrupt occurs.

When the PIT generates an interrupt (e.g., IRQ0 for the system timer), it uses the IDT to find the address of the ISR that should handle the interrupt. If the IDT is not set up:

• The CPU will likely trigger a General Protection Fault (GPF) or triple fault and reset, as it cannot find a valid ISR to handle the interrupt.
• Your system will not correctly handle the timer interrupts, making it impossible to implement a timer or other interrupt-driven functionalities.

So make sure you have the working IDT before doing the steps ahead.

1 Calculate the divisor value:

• The 8253 PIT operates with an input clock frequency of 1.193182 MHz. Which means It ticks for 1193182 times per second.
• We can calculate the correct divisor based on the clock frequency of the PIT.

The divisor is calculated using the formula:

Divisor = Clock Frequency / Desired Frequency

The desired frequency can be calculated as:

Desired Frequency = 1/5 Hz (Since we want one tick every 5 seconds)

Desired Frequency = 1 / 5 Hz = 0.2 Hz
Divisor = 1193182 / 0.2 = 5,965,910

Therefore, the correct divisor for a 5-second interval is 5,965,910.

Or simply we can find the divisor as my way:

Since PIT ticks for 1193182 times per seconds (1.193182 MHz).
So if we want a timer of 5 seconds simply multiply by 5.
1,193,182 * 5  = 5,965,910

2 Set up the PIT mode:

• Select the counter (usually counter 0 for system timer).
• Choose the mode (typically mode 3 for square wave generation).
• Write the divisor value to the counter.

; Set up 8253 PIT for a 5-second interval

MOV AL, 36H     ; Control word: counter 0, mode 3, binary
				; 00110110b = 36H
                ; Bits: 00 (SC0, SC1) - Select Counter 0
                ;       11 (RW0, RW1) - Read/Write LSB followed by MSB
                ;       011 (M2, M1, M0) - Mode 3 (Square Wave Generator)
                ;       0 (BCD) - Binary mode


OUT 43H, AL         ; Send control word to control register

MOV BX, 5965910     ; Load the divisor value

; Send the low byte of the divisor
MOV AL, BL          ; Load low byte of divisor
OUT 40H, AL         ; Send low byte to counter 0


; Send the high byte of the divisor
MOV AL, BH          ; Load high byte of divisor
OUT 40H, AL         ; Send high byte to counter 0

; Counter 0 is now set for a 5-second interval

Explanation:

• Control Word:
  • MOV AL, 36H: Sets up counter 0 in mode 3 (square wave generator) with binary counting.
  • OUT 43H, AL: Sends the control word to the PIT control register (port 43H).
• Divisor Value:
  • MOV BX, 5965910: Loads the calculated divisor value into register BX.
  • MOV AL, BL and OUT 40H, AL: Sends the low byte of the divisor to counter 0.
  • MOV AL, BH and OUT 40H, AL: Sends the high byte of the divisor to counter 0.